a. Field of the Invention
The present invention pertains to the design of electronic circuits and specifically to preparations necessary to perform static timing analyses.
b. Description of the Background
Static timing analysis is a method whereby the performance of an electronic circuit may be estimated. In many cases, a circuit may be used in various modes, such as at different clock speeds or with different multiplexer settings. For each mode, a different static timing analysis must be performed.
The general process for performing static timing analysis is to prepare a netlist that contains all of the nodes of a circuit and simulate the performance of the circuit using an analysis tool. A netlist includes the various components and their connections to each other to define the circuit. A static timing analysis script may be generated that defines the conditions for the static timing analysis to be used by the analysis tool. Such a script may include setting specific registers to specific values or initializing specific clocks in a specific manner.
For complex circuits, many clocks and registers may have to be initialized in order to perform a specific timing analysis. For example, a circuit may have the capability to operate a data bus according to two different standards. Each of the data bus standards may require a specific clock speed and may also require certain sections of the circuit to be active and configured in a certain manner.
Static timing analyses, as well as other simulations of the circuit, are performed many times during the course of designing and developing the circuit. As the circuit is tested and developed, the designer may need to run an analysis with the circuit in one mode, then switch to a different mode and run another analysis immediately thereafter.
As the complexity of the circuit grows, the various settings for switching between modes may be placed in several different places throughout the circuit. When one engineer is responsible for the design, that engineer may be able to have a full comprehension of all the settings and their various locations throughout the design. When several engineers are involved, such as when several engineers work simultaneously or when one takes over the design task from another, there may not be a cognizant engineer with knowledge of all the required settings to switch modes.
It would therefore be advantageous to provide a system and method for setting the various modes or clock settings of an electronic circuit that may be used throughout the design development phase. It would further be advantageous to have an analysis system and method that is simple to use and easily communicated. It would further be advantageous to have an analysis system and method that does not interfere with the final version of the circuit.